Designing Digital Systems With SystemVerilog

This textbook is for a university freshman/sophomore course on digital logic and digital systems design. In addition, the SystemVerilog language is interwoven throughout the text, providing both new learners as well as existing digital logic designers an introduction to the SystemVerilog language and its use for designing digital systems.

Digital design topics include: binary number representations and arithmetic, Boolean Algebra and truth tables, combinational logic circuits, logic minimization, latches and flip flops, registers, counters, state graphs, finite state machines, and FPGA devices.

SystemVerilog topics include: gate-level design, structural design, dataflow assignments, combinational and sequential always blocks and their use, the design of registers, counters, and finite state machines using SystemVerilog.

The book concludes with three fully worked SystemVerilog examples of digital designs: debouncing a switch, a soda machine controller, and a UART.

Table of Contents

Chapter 1. Introduction to Digital Systems Design
Chapter 2. Number Systems and Binary Encodings
Chapter 3. Signed Number Representations, Negation, and Arithmetic
Chapter 4. Boolean Algebra and Truth Tables
Chapter 5. Gates
Chapter 6. Boolean Algebra – Part II
Chapter 7. Gates – Part II
Chapter 8. An Introduction to Gate-Level Design Using SystemVerilog
Chapter 9. Gate-Level Arithmetic
Chapter 10. Higher Level Building Blocks: Multiplexers, Decoders, and Lookup Tables
Chapter 11. Continuing on With SystemVerilog – Hierarchical Design, Constants, and Multi-Bit Signals
Chapter 12. Karnaugh Maps
Chapter 13. Gate Delays and Timing in Combinational Circuits
Chapter 14. Dataflow SystemVerilog
Chapter 15. Latches and Flip Flops
Chapter 16. Registers and RTL-Based Design
Chapter 17. Behavioral SystemVerilog for Registers
Chapter 18. Modeling Combinational Logic Using Behavioral SystemVerilog
Chapter 19. Memories
Chapter 20. Simple Sequential Circuits: Counters
Chapter 21. State Graphs
Chapter 22. Finite State Machines
Chapter 23. State Machine Design Using SystemVerilog
Chapter 24. Asynchronous Input Handling
Chapter 25. Field Programmable Gate Arrays (FPGAs) – An Introduction
Chapter 26. Case Study – Debouncing Switches and Detecting Edges
Chapter 27. Case Study: A Soda Machine Controller
Chapter 28. Case Study: The Design of a UART
Chapter 29. SystemVerilog vs. Verilog
Appendix ASCII Table