The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

The UVM Primer uses simple, runnable code examples, accessible analogies, and an easy-to-read style to introduce you to the foundation of the Universal Verification Methodology. You will learn the basics of object-oriented programming with SystemVerilog and build upon that foundation to learn how to design testbenches using the UVM. Use the UVM Primer to brush up on your UVM knowledge before a job interview to be able to confidently answer questions such as “What is a uvm_agent?” , “How do you use uvm_sequences?”, and “When do you use the UVM’s factory.” The UVM Primer’s downloadable code examples give you hands-on experience with real UVM code. Ray Salemi uses online videos (on uvmprimer.com) to walk through the code from each chapter and build your confidence. Read The UVM Primer today and start down the path to the UVM.

Table of Contents

Chapter 1. Introduction
Chapter 2. A Conventional Testbench for the TinyALU
Chapter 3. SystemVerilog Interfaces and Bus Functional Models
Chapter 4. Object-Oriented Programming (OOP)
Chapter 5. Classes and Extension
Chapter 6. Polymorphism
Chapter 7. Static Methods and Variables
Chapter 8. Parameterized Class Definitions
Chapter 9. The Factory Pattern
Chapter 10. An Object-Oriented Testbench
Chapter 11. UVM Tests
Chapter 12. UVM Components
Chapter 13. UVM Environments
Chapter 14. A New Paradigm
Chapter 15. Talking to Multiple Objects
Chapter 16. Using Analysis Ports in a Testbench
Chapter 17. Interthread Communication
Chapter 18. Put and Get Ports in Action
Chapter 19. UVM Reporting
Chapter 20. Class Hierarchies and Deep Operations
Chapter 21. UVM Transactions
Chapter 22. UVM Agents
Chapter 23. UVM Sequences
Chapter 24. Onward with the UVM